Search: HBM memory scaling

SK hynix unveils 'iHBM' thermal architecture that cools AI memory at the source — integrated cooling elements inside HBM interface cut thermal resistance by 30%, target next-gen HBM5 accelerators and dense AI data centers

… The company believes that structurally preventing thermal throttling will enable next-generation memory layers targeted for future generations like HBM5 to scale to higher stack heights and sustain maximum data transfer speeds under the heavy computational loads of AI data centers. “iHBM is the opt… …

May 26, 2026 · Etiido Uko

Google reportedly books Intel for packaging more than 3 million TPUs in 2028 — SK hynix is testing Intel's EMIB packaging for HBM integration

… HBM stacks are themselves a packaging problem: multiple memory dies bonded vertically through TSVs, then mounted next to a host processor with tight tolerances on power and thermal behavior. …

Jun 10, 2026 · Luke James

Micron's Virginia fab begins producing America's most advanced DRAM memory — fab expansion to quadruple output, easing DDR4 shortage for automotive and defense sectors

… Micron is scaling up DDR4 production as the supply of the older memory standard has become unexpectedly tight. All three major DRAM producers are reallocating fab capacity toward DDR5, LPDDR5X, and high bandwidth memory HBM to meet AI-driven demand from hyperscalers and data center operators. …

May 23, 2026 · Luke James

The custom AI ASIC state of play (May 2026) — Broadcom deals, Google TPUs, Meta MTIA & beyond

… Each Trainium3 delivers 2.517 PFLOPS FP8 with 144GB HBM3E at 4.9 TB/s bandwidth , roughly double the compute and 1.5 times the memory of its predecessor. The new Trn3 UltraServer packs 144 chips delivering 362 FP8 petaflops with 20.7 TB of memory, a 4.4 times improvement over Trn2 UltraServers. …

May 21, 2026 · Luke James

China bypasses US GPU bans with 1.54-exaflops 'LineShine' supercomputer — CPU-only monster packs 2.4 million Huawei-designed Armv9 cores

… Each chiplet contains four HBM domains and four DDR domains; there are 16 NUMA domains per processor. HBM access is highly sensitive to locality, whereas DDR memory access is more uniform within a die and is shared between clusters. …

May 17, 2026 · Anton Shilov

Record-high pricing pushes SSD and memory makers to borrow $880 million just to afford buying chips — Adata, TeamGroup, and others take on substantial debt to survive shortages

… Go deeper with TH Premium: Memory AI data centers are swallowing the world's memory and storage supply The future of DRAM: From DDR5 to future ICs High-bandwidth memory roadmap Here's why HBM is coming for your PC's RAM Adata is the largest single borrower in the group, having completed a NT$2 bill… …

May 18, 2026 · Luke James

The rise of local agentic computing faces a brutal reality: rising DRAM prices — RTX Spark, Gorgon Halo chips subject to 63% DRAM contract price hike this quarter

… DRAM supply squeeze The local AI PC has become a category defined by how much memory it carries, and it’s scaling that memory up at a time when memory has never cost more. …

Jun 3, 2026 · Luke James

Marvell details vision of optically-interconnected data centers spanning across thousands of kilometers — new interconnects sampling later this year would allow CSPs to pool resources based on workload

… If a workload needs more memory than compute, operators often have to buy additional GPUs just to get the extra HBM , but they may just get memory in the future if Marvell's vision comes to pass. …

Jun 15, 2026 · Anton Shilov

Samsung shows first HBM5 mockup with Heat Path Block cooling

Samsung displayed its first physical mockup of HBM5 memory at Computex 2026 in Taipei. Tom's Hardware dropped by to see its pairing of the eighth-generation AI memory with a new in-package cooling structure it calls Heat Path Block, or HPB. …