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Showing top 11 results for "Intel 18A ramp"

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Intel Xeon 6+ Computex roundtable interview transcript — Kira Boyko and Tim Wilson on 18A wafer allocation, Clearwater Forest, and dropping hyper-threading

18A yield and wafer allocation Clearwater Forest is a multi-process design: the compute tiles are built on I ntel's 18A node , with base tiles on Intel 3 and I/O tiles on Intel 7. Journalist 2: Questions you probably want to ask but won't answer. 18A yield volume for Xeon 6+, progressing? …

Jun 2, 2026 · Jake Roach
tomshardware.com › pc-components › cpus

Intel's one-two punch plan in desktop CPUs is taking shape — Z990 spotted, Nova Lake detailed, ‘Raptor Lake Next’ teased

… One advantage of Intel’s hybrid bonding and advanced packaging is that it can package dies from other foundries, not just those from Intel foundries. That brings us to the second finer point about Nova Lake, which is the node. Originally, the assumption was that Intel would use 18A for Nova Lake. …

Jun 16, 2026 · Jake Roach
tomshardware.com › tech-industry › semiconductors

Tesla hires 17-year Intel veteran responsible for billion-dollar fab startups — Gary Jiang likely chosen to oversee fab efforts for Terafab's licensing of 14A

… Earlier in his Intel career, Jiang held multiple management positions at the company's Ocotillo campus in Chandler, Arizona, where he managed technician teams accountable for startup, ramp, yield, and output for 22nm, 14nm, and 10nm-class process technologies which include Intel 10nm SuperFin and 1… …

Jul 1, 2026 · Anton Shilov