AMD Alveo™ V80 Compute Accelerator
…HBM device delivering 820 GB/s, the card features 4x200G networking, PCIe® Gen4 and Gen5 interfaces, DDR4 DIMM slots for memory expansion, and Mini-Cool Edge I/O (MCIO) connectors to scale…
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Hygon's 128-Core & 512-Thread C86 CPU Targets Intel Xeon With 15% IPC Gain, As China Races to Cut Foreign Chip Reliance
…interconnect Paired with high-speed HBM memory A Fully Integrated Networking Solution For Data Centers The next four chips include a PCIe 5.0 Switch, a Scale-Up Interconnect Switch, a 400G…
Only A Few AI Platforms Can Survive
…And companies will get scale any way they can. And despite what anyone says, the limiting factor is not getting compute engine wafers back from the fab, it is getting HBM memory…
Tensordyne Napier AI Processor Announced with Logarithmic Math
…This is also where rack-scale design matters, since simply adding accelerators does not help if the interconnect, memory, power, or cooling infrastructure becomes the limiting factor. Napier itself is a 3nm…
Numenta and Intel Accelerate Inference
…When running large deep learning models at scale, typically memory bandwidth becomes the scaling limiter. HBM triples the memory bandwidth, allowing Numenta to better leverage the computational resources. This is where the…
Marvell details vision of optically-interconnected data centers spanning across thousands of kilometers — new interconnects sampling later this year would allow CSPs to pool resources based on workload
…If a workload needs more memory than compute, operators often have to buy additional GPUs just to get the extra HBM , but they may just get memory in the future if Marvell…
The global memory shortage: The hidden bottleneck behind the AI boom
…HBM now directly shapes who can scale AI deployments, how quickly they can bring new capabilities online and at what cost. This marks a stark change from the past, when memory sat…
Micron Samples 256GB DDR5 RDIMMs With Blistering 9200 MT/s Speeds for AI
…Micron is utilizing 3D stacking, connecting multiple memory dies vertically using through-silicon vias (TSVs), just like with HBM or AMD's 3D V-Cache . This essentially builds little skyscrapers of memory…
Qualcomm Investor Day 2026 Data Center Announcements CPUs, AI Accelerators, and More
…Instead of HBM over CoWoS interposer, Qualcomm is saying that it will stack memory on top of compute tiles. Details are a bit light, but it seems like 768GB or so of…
Kyoto University Enhances HPC Performance
…However, solutions that implement HBM and achieve high memory bandwidth will inevitably be expensive. Therefore, at Intel, we understand the requirements and are considering various new memory technologies. In the near future…